Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation

The article introduces STG, a Structured Testbench Generation framework designed to enhance automated testbench generation for hardware designs in LLM-driven RTL workflows. STG offers deterministic outputs, achieving a 720x speed increase over traditional LLM-based methods, higher verification coverage, and reduced false-pass rates. Additionally, it serves as an efficient data curation engine, operating 11x faster with significantly lower energy consumption and improved performance in multi-benchmark evaluations, making it a valuable tool for practitioners in hardware verification and design.