VeriPilot: An LLM-Powered Verilog Debugging Framework

VeriPilot is a newly proposed LLM-powered framework designed to enhance Verilog debugging by utilizing golden reference models for effective bug localization and repair. It employs Control-Data-Flow Graphs (CDFGs) derived from static analysis to facilitate step-by-step signal tracing, significantly improving the bug repair success rate of GPT-4o from 54.3% to 85.71% on the Comprehensive Verilog Design Problems (CVDP) benchmark. This advancement addresses the challenge of tracing long dependency chains in complex codebases, making it a valuable tool for practitioners in digital circuit design.