VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation

VHDLSuite has been introduced as a comprehensive framework for evaluating Large Language Models (LLMs) in the context of VHDL code generation. It features an automated data pipeline that converts Verilog designs into VHDL benchmarks, alongside VUnit/GHDL validation to ensure functionality. The suite includes VHDLBench, which comprises over 200 validated VHDL problems, facilitating extensive evaluation of LLMs and highlighting challenges in VHDL generation, thus advancing the understanding of multi-language hardware design automation.