Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement

The paper presents a framework for hardware generation that integrates large language models (LLMs) with formal methods to ensure correctness in register-transfer level (RTL) design. It introduces a set of transformation rules that guide the LLM in converting design specifications into RTL code while minimizing errors. This approach addresses the concerns of hardware engineers regarding LLM hallucinations, making it a significant advancement for practitioners in chip design and manufacturing who require reliable and interpretable outputs.