AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting

AUTOGATE is introduced as the first automated framework for fine-grain clock gating (FGCG) in RTL power optimization, addressing the limitations of existing LLM-based approaches. It employs a machine learning-based clustering algorithm to convert raw toggling traces into structured representations, which guide LLM-driven RTL rewriting without direct waveform processing. The framework demonstrates significant power reductions, achieving an average of 49.31% on small designs and 19.34% on the NVDLA industrial design, making it a valuable tool for practitioners seeking efficient dynamic power management in large hierarchical codebases.